This invention relates, in general to semiconductor devices, including, but not limited, to a method of making a substantially planar semiconductor surface for semiconductor devices.
Bipolar and complimentary MOS (BiCMOS) devices are fabricated in a semiconductor structure which is comprised of a semiconductor substrate, having P-type and N-type buried layers formed in the substrate and an epitaxial layer formed on the substrate. An n-type well is formed in the epitaxial layer, followed by the formation of a p-type well. In the process of forming the buried layers and the wells, a differential step height is formed at the surface of the epitaxial layer between the N-type well and the P-type well (i.e. twin wells). This differential step height can cause depth of focus problems in the photolithographic steps. This had not been a major problem in devices with feature sizes greater than approximately a micron, however, it is a major problem in devices with submicron feature sizes. Depth of focus problems during processing ultimately can result in poor electrical characteristics and reduced yield in the submicron BiCMOS device.
In addition to the depth of focus problem, the differential step height in the semiconductor surface results in contact etching problems for deep submicron technologies. In general, it is desirable to planarize the device structure prior to deposition of a metal layer in order to facilitate patterning of submicron metal features. This planarization is accomplished by using planarizing dielectrics. When planarizing dielectrics are used on a structure having a differential step height in the semiconductor surface, along with the normal step height differentials in different areas of the device structure, it is difficult to remove portions of the planarizing dielectric to make contact to an underlying layer without removing a certain amount of that underlying layer in the areas where the planarizing dielectric layer is the thinnest. A way to solve this problem would be not to use planarizing dielectrics. This solution is not acceptable because it is undesirable to have non planar devices for deep submicron technologies.
Accordingly, it would be desirable to eliminate the differential step height created in the epitaxial layer to eliminate the depth of focus problem and the contact etching problem in submicron BiCMOS devices. In general, it would be desirable to eliminate the step height differential without unduly complicating the BiCMOS process.